Known equipment for the testing of electrochemical energy generating and storage devices, such as fuel cells and batteries, suffer from one or more of several drawbacks. For example, known testing systems provide inadequate control of the amount of energy consumed in a load under test coupled to such an energy source. The present invention provides a resistive load used to controllably consume the electrical energy produced or stored by an electrochemical device.
The simplest known system, now rarely used, provides a network of switches and resistors as a test load. Each resistor is in series with a switch, and each resistor-switch pair is in parallel with all of the others. As each switch is closed, the total resistance of the network drops. The resistors may be identical in resistance, or they may provide different resistances to allow finer control of the total resistance of the load. Such a system includes a large number of mechanical contacts brought to the circuit with the switches. Each mechanical contact adds a varied and changing resistance to the network. In a large network, consisting of a dozen or more switches, the network resistance will seldom be exactly the same twice. The unavoidable mechanical wear that occurs during use of such a system only adds to the problem by changing the resistance of different switches differently. Such a system may be improved by the addition of a variable potentiometer in parallel with the switches, but this only replaces one set of mechanical components for another, with all its inherent drawbacks.
The test array just described may be improved by replacing the switches and resistors with field effect transistors (FETs). An FET is a voltage controlled device having a linear region of its operating characteristic and a saturated region at higher input voltages. In the linear region, a FET emulates a resistor having a resistance that can be varied over a wide range through the application of a bias voltage to one terminal of the device. In its simplest form, an FET-based electronic load, which generally consists of a set of FETs mounted in parallel, is controlled by manually adjusting the gate voltage to produce the desired current flow through the system. This system is a distinct improvement on a resistor network. It eliminates the switch contact problems and provides virtually infinite variability in resistance over the available load range. However, such a system requires manual operation to change the output of the system including periodic readjustments to offset variations produced by thermal effects in the circuit or variations in the performance of the source under test.
The circuit can be stabilized by the addition of analog circuitry tuned to measure and compensate for the external changes. This circuit can be sufficiently complex to hold a constant current through changes in the performance of the device under test and to provide for external control of the load via an analog voltage supplied from an external source. A load of this type permits automation of the test system, however it is relatively complex. The large number of components involved increases the difficulty in fabrication and increases the chance of at least one component malfunctioning. The difficulty in fabrication and the number of components make this system expensive to produce and difficult to maintain.
Commercially available electronic loads such as those produced by Hewlett Packard, have been used as loads for fuel cell and battery testing. While they are a distinct improvement on the loads described above, they are still deficient in several respects. They typically have maximum current capabilities on the order of 120 amps. While this is adequate for the uses they were designed for, it is insufficient for a high power density fuel cell. A 50 cm.sup.2 fuel cell operating at 3 A/cm.sup.2 puts out 150 Amps, and some systems are routinely operated at up to 4 A/cm.sup.2, while many developers use cells with larger areas. These units also have a second deficiency when used to test either single cell fuel cells or batteries. Since they were not designed for fuel cell testing or single cell battery testing, they were designed to operate with a typical minimum potential of 3 Volts. If operated at lower voltages, the maximum current capacity is substantially reduced. Most fuel cells reach their maximum power output at around 0.6 Volts, and at this voltage a 120 Amp load's capacity is reduced to about 40 Amps. This can be overcome by placing a power supply in series with the fuel cell or battery being tested to boost the voltage. While this works, there is some risk involved. For instance, when the device under test is a fuel cell, if the gas supply to a fuel cell is cut off, the cell voltage can go to zero. Since the power supply is still applying a voltage, it is possible for the cell to be forced into reverse and become an electrolyzer. In this mode the cell will generate hydrogen in the compartment that had previously contained oxygen, and oxygen in the one that had contained hydrogen. This can form an explosive mixture in either compartment. This is a situation that is to be avoided.
Still another type of electronic load can be constructed using a high speed chopper to turn the current through a fixed resistor on and off at high frequency (&gt;1000 Hz). When the chopper is on, the current flows at the same level as if the resistor were connected directly to the fuel cell. When the chopper is off the current flow is zero. The duty cycle of the chopper is adjusted so that the total coulomb flux each second is the same as it would be through a fixed resistance larger than that of the actual resistor. One problem with this approach is that a fuel cell responds quite quickly to changes in resistance and tries to track the load. This can bias the results obtained in two ways. One of these is that a fuels cell's performance in a cycling system is not always the same as in a steady state system, even if the two systems have the same time averaged performance. Many types of batteries also show better performance under an intermittent load than a steady one and produce an overly optimistic result when tested under these conditions. The other bias is not in the cell, but in the measurement of the cell voltage under load with a fluctuating load. If the voltmeter being used doesn't average the voltage correctly at the chopper frequency being used the results will be incorrect. For example, a DC voltmeter used to measure a high frequency AC voltage will give a reading greater than the true root mean square (RMS) value, and this will lead to an overly optimistic and inaccurate result.
U.S. Pat. No. 5,512,831 (Cisar) teaches a controlled resistive load consisting of field effect transistors (FETs) operated in the linear region allowing them to function simply as a variable resistor. To increase the power dissipating or current carrying capacity of the overall load, a number of these matched FETs are placed electronically in parallel such that they share the load unifonnly. Both the control signal and the applied current are connected in parallel, allowing the multitude of FETs to be controlled in unison by a single external electronic command.
In addition to a conventional FET based load, Cisar further adds the feature that the transistors are placed in a computer controlled feedback loop, in this feedback loop, a command signal is used to place the FETs in a predetermined location in their linear region where they will have a known resistance. The overall current through the electronic load is then measured and this signal digitized and sent back to the controlling computer. The controlling computer then trims or adjusts the FET control signal so that the measured current approaches the desired current. This control loop continues until the desired current is achieved in an iterative manner.
This type of load control operates in both theory and practice and has been demonstrated to be an effective means of accurately applying an electronically controlled load to an electrochemical energy conversion device. However the system suffers from two limitations; the first is merely a limitation in the performance while the second is a limitation in the durability of the components and system.
The first limitation stems from the slow, albeit controlled, response to changes in the applied load. This is entirely due to the time delay of having a purely digital control and feedback system, and from the iterative approach to finding the target resistance.
The second limitation is more critical in that as the initially matched FETs age, their characteristics change. Most importantly, a significant FET to FET variance in their turn-on voltage (which is already significantly wider than bipolar transistors since it is a difficult parameter to control in the production of the FET) will occur, changing the amount of current passed through the FET for a given gate voltage. For this particular application where the FETs are operated in parallel and primarily in their linear region, the matching of each FET's resistance versus the applied control voltage is extremely critical. Since each FET is given the same control voltage, any mismatch in the response to that control voltage will result in an individual FET having a higher or lower terminal resistance than the average of the entire FET bank. As expected from Ohm's law, the FETs having the lower resistance will shunt more of the current while the FETs having the higher resistance will shunt less current. To partially alleviate this problem, FETs have a positive temperature coefficient over the upper current portion of their operating range, meaning that as they get hotter, their resistance increases. This is in contrast to bipolar transistors which are more difficult to use in parallel because they have a negative temperature coefficient, i.e., their resistance decreases as their temperature increases. Therefore operating FETs in parallel over the saturated region is generally self limiting, i.e., the transistor that begins carrying additional current becomes hotter, resulting in a higher resistance and, in turn, resulting in a reduced current. Bipolar transistors, however, exhibit thermal runaway since as the component heats, its resistance decreases, further increasing the current through the device, and therefore further heating the device.
The difficulty in operating FETs in parallel occurs at their lower gate voltages and current settings since FETs have a negative temperature coefficient in that portion of their operating mode. In this low gate voltage region FETs exhibit thermal runaway just as exhibited by bipolar transistors. However, for the purpose of testing low voltage, high current devices (such as batteries and fuel cells), a large number of FETs must be placed in parallel to minimize their overall resistance. During operation of a load under low current conditions, these FETs are required to be at the very bottom of their linear region where the negative temperature coefficient is the largest. Therefore, a means of modifying the low current characteristics of each individual FET is necessary to prevent thermal runaway over the entire range of operation of the ultra-low resistance electronic load.
The most critical operating points are when the FETs are just above their threshold voltage where they are just beginning to turn on, and when they are approaching the boundaries of their safe operating area (SOA), beyond which they may become damaged or their operating lifetime shortened.
Therefore, methods of modifying the characteristics of FETs are required to prevent any individual component from passing excessive current which may shorten the component lifetime, change its operating characteristics, or cause it to be otherwise damaged or destroyed. Two methods of circuit compensation are generally used. Passive control, where passive components such as resistors, diodes, etc., are used, and active control where components such as transistors, op-amps, etc., are used.
One passive method utilizes components having a parameter, such as resistance, which is known to vary in a controlled and predictable manner in response to a second parameter such as temperature. In the low current portion of operation, FETs themselves are an example of a device having a negative temperature coefficient. In that region, at a given gate voltage FETs tend to become less resistive as their temperature increases and will therefore pass more current if the gate voltage and the applied voltage at the source and drain remain fixed. Utilizing one or more additional components having temperature coefficients opposite to, or the same as, the FET, allows a temperature compensating circuit to be constructed. This circuit can then be used to modify the behavior of the FET so that the performance of the FET remains predictable and preferably operates with a positive temperature coefficient over its entire range of operation. In this manner, the voltage being applied at the gate of the FET can be made to change in a manner that produces an overall effect that is comparable to, or larger than, any negative temperature coefficient inherent to FETs. This compensation modifies the gate voltage being applied to those FETs as they change temperature, allowing the FETs to participate equally in the current sharing of the load. A number of factors may be used to control the compensating circuit, most obvious of which are the current through the FET and the temperature of the FET.
A second method to match component characteristics is to modify the voltage being applied to the gate through an active means such as an operational amplifier (op-amp). In this active method of component matching, once again a component parameter, such as temperature, current, or voltage drop, is used to trim the gate voltage and therefore bring the FET resistance closer to the others in the load. This may be accomplished by placing the FET within a feedback circuit and using the result of that feedback circuit to control the FET. From there it is quite straightforward to implement an active circuit which prevents the FET from exceeding the boundaries of its SOA. This may be accomplished by summing with an external signal or otherwise modifying the gate voltage so that the maximum allowable current through the FET remains under a predetermined level.
However, it should be remembered that any number of parameters must remain within a window of operation if the FET is to perform over a reasonable lifetime. These include maximum power dissipation, gate voltage, applied forward voltage, reverse voltage, and temperature among others. When operated as an electronic load the FET must be operated in the safe operating area which may depend upon multiple parameters. As the limits of the SOA depends upon multiple factors, it becomes extremely difficult for a simple analog circuit to trim and adjust the relative current through each component as the number of input variables increases. As an example, the most common cause of exceeding the SOA in an electronic load are current and power dissipation but the boundaries of the SOA depend upon these variables as well as the source-drain voltage and the temperature of the FET itself. Therefore, a more sophisticated method of FET protection is needed when FETs are used in parallel for an electronic load. The preferred method will take all parameters into account to determine if any individual FET is approaching the SOA boundary, and prevent that single FET from leaving the SOA while continuing to manage the operation of the entire load.